Power efficient Simulation of Diminished-One Modulo 2n+1 Adder Using Circular Carry Selection
نویسندگان
چکیده
In this paper we have find great applicability in RNS implementation for the Diminished-one modulo 2n+1 Adder using Circular Carry Selection (CCS) circuit. This adder presents a modulo addition of different bit values for n = 8, 12, 16, 24, 32, 48, 64. We are using the Diminished-one criteria using Circular Carry Selection (CCS) technique for the proposed modulo adder. The circuit design of proposed adder consists of a Dual Sum-Carry Look Ahead Adder (DS-CLA), a Circular Carry Generator (CCG) and a Multiplexer (MUX). Results are verified by verilog HDL programs and performance parameters are observed on Synopsys Design Complier using the TSMC (180nm and 90nm) implementation technology. We have calculated the area, power dissipation and Time delay and results are compared with Select-Prefix method for n = 8, 16, 32 and 64 and found that the proposed adder has more area efficient than Select-Prefix Method. Keyword VLSI Design, Residue Number System (RNS), Modulo 2n+1 Adder, Diminished-one, Circular Carry Selection (CCS), Carry Look Ahead.
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